FIG. 1 is a block diagram illustrating a conventional power control circuit of a CPU in a computer system. The power providing circuit comprises a power supply 12, a pulse-width-modulation (PWM) controller 14, and a CPU 16. The PWM controller 14 is introduced in the computer system because the PWM controller 14 can dynamically modulate the core voltage (Vcore) to the CPU 16 according to the real-time load of the CPU 16. In other words, the PWM controller 14 can provide a relative large core voltage (Vcore) to the CPU 16 if the load of the CPU 16 is relative high; and, the PWM controller 14 can provide a relative small core voltage (Vcore) to the CPU 16 if the load of the CPU 16 is relative low. The real-time road of the CPU 16 can be aware of via a voltage identification (VID) signal that is outputted from the CPU 16, where the CPU capable of outputting the VID signal is categorized to a CPU with the Enhance Intel Speed Step Technology (EIST) function that is developed by Intel. Via the VID signal, the PWM controller 14 can detect the real-time load of the CPU 16 and dynamically modulate the core voltage (Vcore) to the CPU 16 if the CPU 16 has the EIST function.
If the load of the CPU is extremely high, the clock frequency of the CPU is defined in the highest-frequency mode (HFM) and the power consumption of the CPU is defined at a largest value. If the load of the CPU is extremely low, the clock frequency of the CPU is defined in the lowest-frequency mode (LFM) and the power consumption of the CPU is defined at a smallest value. However, the CPU is not limited to operate at the clock frequency in the range between the highest-frequency mode (HFM) and the lowest-frequency mode (LFM). According to the practical operations or experiments, the CPU can work normally if the clock frequency applied to the CPU is higher than the clock frequency in the highest-frequency mode (HFM). In other words, the CPU not only can work normally but also has a better performance if the clock frequency is raised up 10% or 20% higher than the clock frequency in the highest-frequency mode (HFM), where operating the CPU at a clock frequency higher than the clock frequency in the highest-frequency mode (HFM) is defined as an over clocking. Similarly, the CPU can work normally if the clock frequency applied to the CPU is lower than the clock frequency in the lowest-frequency mode (LFM). In other words, the CPU not only can work normally but also has a better power saving if the clock frequency is lowered down 10% or 20% less than the clock frequency in the lowest-frequency mode (LFM), where operating the CPU at a clock frequency lower than the clock frequency in the lowest-frequency mode (LFM) is defined as an under clocking.
Besides, the over clocking/or the under clocking must be accompanied with the modulation of the core voltage (Vcore) and the core voltage (Vcore) is necessary modulated first before the modulation of the clock frequency according to the specification of CPU. In other words, before executing the over clocking to the CPU, the core voltage (Vcore) applied to the CPU must be raised up first. On the contrary, it needs to execute the under clocking to the CPU first, the core voltage (Vcore) applied to the CPU be lowered down.
FIG. 2 is a block diagram illustrating a conventional computer system executing the over clocking/or under clocking to a CPU. The computer system comprises a power supply 22, a PWM controller 24, a CPU 26, a control device 28, a basic-input-output-system (BIOS) 30, a clock-frequency generator 32, and an application program 34. If user desires a better performance of the computer system and plans to execute the over clocking to the CPU 26, the raising up of the core voltage (Vcore) applied to the CPU 26 must be done first. User can rise up the core voltage (Vcore) via a setup menu of the BIOS 30. That is, user can select a relative high core voltage (Vcore) provided by the setup menu of the BIOS 30. Once the relative high core voltage (Vcore) on the setup menu of the BIOS 30 is selected, the BIOS 30 then informs the control device 28 to ask the PWM controller 24 to provide the relative high core voltage (Vcore) to the CPU 26 when the computer system entering to the operation system (OS) next time. Because the core voltage (Vcore) is modulated to higher, then user can execute the over clocking (10% or 20% higher than the highest-frequency mode (HFM)). The over clocking can be executed via the application program 34. Once a relative high clock frequency is selected (or key-in) in the application program 34, a relative high clock frequency (CLKCPU) is then outputted to the CPU 26 from the clock-frequency generator 32, so as the over clocking of the CPU 26 is done.
Similarly, if user desires a better power saving of the computer system and plans to execute the under clocking to the CPU 26, the lowering down of the core voltage (Vcore) applied to the CPU 26 must be done after executing the under clocking. The lowering down of the core voltage (Vcore) can be done according to the same manner described above in the process of rising up of the core voltage (Vcore), so as no unnecessary details are given here.
However, once the core voltage (Vcore) is selected via the BIOS 30 and the computer system enters to the operation system (OS), the core voltage (Vcore) cannot be modulated again unless the computer system entering to the BIOS 30 again. In other words, once the relative high core voltage (Vcore) is selected by user based on a desire of a better performance, a power waste may be happened if the CPU is not necessary to operate at the relative high core voltage (Vcore). Similarly, once the relative low core voltage (Vcore) is selected by user based on a desire of power saving, a poor performance may be happened if the CPU cannot obtain enough core voltage (Vcore).
Furthermore, according to the specification of CPU, the core voltage (Vcore) is necessary to raise up before the execution of the over clocking to CPU and the core voltage (Vcore) is necessary to lower down after the execution of the under clocking to CPU. However, according to the practical operations and experiments, the raising up/or the lowering down of the core voltage (Vcore) is not necessary to accompany with the over clocking/or the under clocking. In other words, user still can execute the over clocking to the CPU without rising up the core voltage (Vcore). In some special computer systems, the over clocking of the CPU even can be done if the core voltage (Vcore) is lowered down.
Furthermore, because the relative old version of the CPU is without EIST function and cannot output the VID signal, the conventional process of the modulation of the core voltage (Vcore)/clock frequency cannot be applied to the CPUs without the EIST function.